HC20K400 Datasheet, PDF (12/36 Pages) Altera Corporation – HardCopy APEX Device Family

HardCopy Series Handbook, Volume 1
Table 8–2. HardCopy APEX Device Features (Part 2 of 2)
Feature
HardCopy Devices
ClockLock support
Clock delay reduction
m /(n × v) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift circuitry
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Dedicated clock and input pins Eight
I/O standard support
1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
3.3-V PCI and PCI-X
3.3-V AGP
CTT
GTL+
LVCMOS
LVTTL
True-LVDS and LVPECL data pins
LVDS and LVPECL clock pins
HSTL class I
PCI-X
SSTL-2 class I and II
SSTL-3 class I and II
Memory support
CAM
Dual-port RAM
FIFO
RAM
ROM
f
All HardCopy APEX devices are tested using automatic test pattern
generation (ATPG) vectors prior to shipment. For fully synchronous
designs near 100%, fault coverage can be achieved through the built-in
full-scan architecture. ATPG vectors allow the designer to focus on
simulation and design verification.
Because the configuration of HardCopy APEX devices is built-in during
manufacture, they cannot be configured in-system. However, if the
APEX 20KE or APEC 20KC device configuration sequence must be
emulated, the HardCopy APEX device has this capability.
All of the device features of APEX 20KE and APEX 20KC devices are
available in HardCopy APEX devices. For a detailed description of these
device features, refer to the APEX 20K Programmable Logic Device Family
Data Sheet and the APEX 20KC Programmable Logic Device Family Data
Sheet.
8–4
Altera Corporation
September 2008