HC20K400 Datasheet, PDF (23/36 Pages) Altera Corporation – HardCopy APEX Device Family

Recommended Operating Conditions
Table 10–3. HardCopy APEX Device DC Operating Conditions (Part 2 of 2) Notes (6), (7), (8)
Symbol
Parameter
R _CONF
Value of I/O pin pull-up
resistor before and during
configuration emulation
Conditions
V_CCIO = 3.0 V (12)
V_CCIO = 2.375 V (12)
V_CCIO = 1.71 V (12)
Min
Typ
Max
Unit
20
50
kΩ
30
80
kΩ
60
150
kΩ
Table 10–4. HardCopy APEX Device Capacitance Note (13)
Symbol
Parameter
Conditions
Min
Typ Max
C_IN
C_{INC LK}
C_OUT
Input capacitance
Input capacitance on
dedicated clock pin
Output capacitance
V_IN = 0 V, f = 1.0 MHz
V_IN = 0 V, f = 1.0 MHz
V_OUT = 0 V, f = 1.0 MHz
8
pF
12
pF
8
pF
Notes to Table 10–1 through 10–4:
(1) Refer to the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum V_CC rise time is 100 ms, and V_CC must rise monotonically.
(5) All pins (including dedicated inputs, clock, I/O, and JTAG pins) may be driven before V_CCINT and V_CCIO are
powered.
(6) Typical values are for T_A = 25° C, V_CCINT = 1.8 V, and V_CCIO = 1.8 V, 2.5 V, or 3.3 V.
(7) These values are specified under the HardCopy device recommended operating conditions, as shown in Table 10–2
on page 10–1.
(8) Refer to AN 117: Using Selectable I/O Standards in Altera Devices for the V_IH, V_IL, V_OH, V_OL, and I_I parameters when
V_CCIO = 1.8 V.
(9) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
(10) The I_OH parameter refers to high-level TTL, PCI, or CMOS output current.
(11) This value is specified for normal device operation. The value may vary during power-up.
(12) Pin pull-up resistance values will be lower if an external source drives the pin higher than V_CCIO.
(13) Capacitance is sample-tested only.
Altera Corporation
September 2008
10–3