HC20K400 Datasheet, PDF (19/36 Pages) Altera Corporation – HardCopy APEX Device Family

Document Revision History
Table 9–4 shows the JTAG timing parameters and values for HardCopy
devices.
Table 9–4. HardCopy APEX JTAG Timing Parameters and Values
Symbol
Parameter
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
t_JSXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Min Max Unit
100
ns
50
ns
50
ns
20
ns
45
ns
25 ns
25 ns
25 ns
20
ns
45
ns
35 ns
35 ns
35 ns
f
For more information about using JTAG BST circuitry in Altera devices,
refer to Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
in Altera Devices.
Document
Table 9–5 shows the revision history for this chapter.
Revision History
Table 9–5. Document Revision History (Part 1 of 2)
Date and Document
Version
Changes Made
September 2008,
v2.3
Updated chapter number and metadata.
June 2007, v2.2
Minor text edits.
December 2006
v2.1
Updated revision history.
March 2006
Formerly chapter 11; no content change.
Summary of Changes
—
—
Updated revision history.
Altera Corporation
9–3
September 2008