HC20K400 Datasheet, PDF (11/36 Pages) Altera Corporation – HardCopy APEX Device Family

Figure 8–1. HardCopy APEX Device Architecture
I/O Elements
PLLs
Introduction
LE
LAB
ESB
Strip of auxiliary
gates (SOAG)
The strip of auxiliary gates (SOAG) is an Altera proprietary feature
designed into the HardCopy APEX device and is used during the
HardCopy device implementation process. The SOAG structures can be
configured into several different types of functions through the use of
metallization. For example, high fanout signals require adequate
buffering, so buffers are built out of SOAG cells for this purpose.
HardCopy APEX devices include the same advanced features as the
APEX 20KE and APEX 20KC devices, such as enhanced I/O standard
support, content-addressable memory (CAM), additional global clocks,
and enhanced ClockLock circuitry. Table 8–2 lists the features included in
HardCopy APEX devices.
Table 8–2. HardCopy APEX Device Features (Part 1 of 2)
Feature
MultiCore system integration
Hot-socketing support
32-/64-bit, 33-MHz PCI
32-/64-bit, 66-MHz PCI
MultiVolt I/O operation
HardCopy Devices
Full support
Full support
Full compliance
Full compliance
1.8-V, 2.5-V, or 3.3-V V_CCIO
V_CCIO selected bank by bank
5.0-V tolerant with use of external resistor
Altera Corporation
8–3
September 2008