HC20K400 Datasheet, PDF (15/36 Pages) Altera Corporation – HardCopy APEX Device Family

Document Revision History
■ The Delay Information File (.sdo) is used to check the original FPGA
timing
■ A completed HardCopy timing requirements file describes all
necessary timing information on the design. A template of this text
file is available for download from the Altera website at
www.altera.com.
The migration process consists of several steps. First, a netlist is
constructed from the SOF. Then, the netlist is checked to ensure that the
built-in scan test structures will operate correctly. The netlist is then fed
into a place-and-route engine, and the design interconnect is generated.
Static timing analysis ensures that all timing constraints are met, and
static functional verification techniques are employed to ensure correct
device migration. After successfully completing these stages, physical
verification of the device takes place, and the metal mask layers are taped
out to fabricate HardCopy APEX devices.
Document
Table 8–3 shows the revision history for this chapter.
Revision History
Table 8–3. Document Revision History
Date and Document
Version
Changes Made
September 2008,
v2.3
Updated chapter number and metadata.
June 2007, v2.2
Minor text edits.
December 2006
v2.1
Updated revision history.
March 2006
January 2005
v2.0
June 2003
v1.0
Formerly chapter 10; no content change.
Update device names and other minor textual changes
Initial release of Chapter 10, Description, Architecture and
Features, in the HardCopy Device Handbook
Summary of Changes
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Altera Corporation
8–7
September 2008