HC20K400 Datasheet, PDF (10/36 Pages) Altera Corporation – HardCopy APEX Device Family

HardCopy Series Handbook, Volume 1
The migration of a FPGA to a HardCopy APEX device begins with a user
design that has been implemented in an APEX 20KE or APEX 20KC
device. Table 8–1 shows the device equivalence for HardCopy and
APEX 20KE or APEX 20KC devices.
Table 8–1. HardCopy and APEX 20KE or APEX 20C Device Equivalence
HardCopy APEX Device
HC20K1500
HC20K1000
HC20K600
HC20K400
APEX 20KE Device
EP20K1500E
EP20K1000E
EP20K600E
EP20K400E
APEX 20KC Device
EP20K1500C
EP20K1000C
EP20K600C
EP20K400C
1 To ensure HardCopy device performance and functionality, the
APEX 20K design must be completely debugged before
committing the design to HardCopy device migration.
HardCopy APEX device implementation begins with extracting the
Quartus II software-generated SRAM Object File (.sof) and converting its
connectivity information into a structural Verilog HDL netlist. This netlist
is then placed and routed in a similar fashion to a gate array. There are no
dedicated routing channels. The router can exploit all available metal
layers (up to four) and route over LE cells and other functional blocks.
Altera’s proprietary architecture and design methodology will guarantee
virtually 100% routing of any APEX 20KE or APEX 20KC design
compiled and fitted successfully using the Quartus II software. Place and
route is timing-driven and will comply with the timing constraints of the
original FPGA design as specified in the Quartus II software. Figure 8–1
shows a diagram of the HardCopy APEX device architecture.
8–2
Altera Corporation
September 2008