AK4637 Datasheet, PDF (92/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
■ Stop of Clock
When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied.
1. PLL Master Mode
PMPLL bit
(Addr:01H, D2)
External MCKI
Input
(1)
(2)
Example:
Audio I/F Format: I2S Compatible (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
(1) Addr:01H, Data:08H
(2) Stop an external MCKI
Figure 75. Clock Stopping Sequence (1)
<Sequence>
(1)Power down PLL: PMPLL bit = “1”  “0”
(2)Stop an external master clock.
2. PLL Slave Mode (BICK pin)
PMPLL bit
(Addr:01H, D2)
External BICK
External FCK
Input
Input
(1)
(2)
(2)
Example
Au: dio I/F Format: I2S Compatible (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 76. Clock Stopping Sequence (2)
<Sequence>
(1)Power down PLL: PMPLL bit = “1”  “0”
(2)Stop an external master clock.
3. EXT Slave Mode
External MCKI
External BICK
External FCK
Input
Input
Input
(1)
Example
:^{Audio I/F Format: I2S Compatible (ADC & DAC)}
(1)
Input MCKI frequency: 256fs
(1) Stop the external clocks
(1)
Figure 77. Clock Stopping Sequence (3)
<Sequence>
(1) Stop the external MCKI, BICK and FCK clocks.
015010680-E-00
- 92 -
2015/09