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AK4637 Datasheet, PDF (55/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP | |||
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[AK4637]
5. Example of registers set-up sequence of ALC Operation
The following registers must not be changed during ALC operation. These bits must be changed after
ALC operation is stopped by ALC bit = â0â. ALC output is â0â data until the AK4637 becomes manual
mode after writing â0â to ALC bit.
LMTH2-0, WTM1-0, RGAIN2-0, REF7-0, RFST1-0, EQFC1-0, FRATT, FRN and ALCEQN bits
Manual Mode
WR (FRATT= â0â, FRN = â0â)
Example:
Recovery Waiting Period = 21.3ms@48kHz
Recovery Gain = 0.00106dB (2/fs)
Fast Recovery Gain = 0.0032dB
Maximum Gain = +30.0dB
Gain of IVOL = +30.0dB
Limiter Detection Level = ï4.1dBFS
EQFC1-0 bits = â10â
ALCEQN bit = â0â
FRATT bit = â0â
FRN bit = â0â
ALC bit = â1â
(1) Addr=09H, Data=00H
WR (EQFC1-0, WTM1-0, RFST1-0)
(2) Addr=0AH, Data=6CH
WR (REF7-0)
(3) Addr=0CH, Data=E1H
WR (IVOL7-0)
* The value of IVOL should be
the same or smaller than REFâs
(4) Addr=0DH, Data=E1H
WR (ALCEQN = â0â, ALC = â1â, RGAIN2-0, LMTH2-0)
(5) Addr=0BH, Data=2EH
ALC Operation
WR: Write
Figure 47. Registers Set-up Sequence at ALC Operation (Recording path)
015010680-E-00
- 55 -
2015/09
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