AK4637 Datasheet, PDF (89/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
■ Speaker Amplifier Output
FS3-0 bits
(Addr:06H, D3-0)
1011
1011
(1)
(14)
DACS bit
(Addr:02H, D5)
(2)
SPKG1-0 bits
00
01
(Addr:03H, D7-6)
(3)
Timer Select
(Addr:09H)
ALC Setting
(Addr:0AH, 0BH)
00H
(4)
60H, 00H
(5)
00H
6CH, 2EH
REF7-0 bitsl
(Addr:0CH)
E1H
(6)
A1H
IVOL7-0 bits
(Addr:0DH)
DVOL7-0 bits
(Addr:10H)
E1H
(7)
18H
(8)
91H
18H
Digital Filter Path
(Addr:18H)
03H
04H
(9)
ALC State
PMPFIL bit
PMDAC bit
(Addr:00H, D2)
PMSL bit
(Addr:01H, D1)
SLPSN bit
(Addr:02H, D7)
ALC Disable
(10)
(11)
ALC Enable
(12)
(13)
> 1 ms
ALC Disable
(16)
(15)
SPP pin
Hi-Z Normal Output Hi-Z
SPN pin
Hi-Z
AVDD/2 Normal Output AVDD/2
Hi-Z
Figure 72. Speaker-Amp Output Sequence
Example:
PLL Master Mode
Audio I/F Format: I2S Compatible
Sampling Frequency: 48KHz
Output Digital Volume: 0dB
ALC setting: Refer to Table 38
Programmable Filter OFF
(1) Addr:06H, Data:0BH
(2) Addr:02H, Data:20H
(3) Addr:03H, Data:40H
(4) Addr:09H, Data:00H
(5) Addr:0AH, Data:6CH
Addr:0BH, Data:2EH
(6) Addr:0CH, Data:A1H
(7) Addr:0DH, Data:91H
(8) Addr:10H, Data:18H
(9) Addr:18H, Data:04H
(10) Addr:00H, Data:C4H
(11) Addr:01H, Data:0EH
(12) Addr:02H, Data:A0H
Playback
(13) Addr:02H, Data:20H
(14) Addr:02H, Data:00H
(15) Addr:01H, Data:0CH
(16) Addr:00H, Data:40H
<Sequence>
At first, clocks must be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4637 is in PLL mode, DAC,
Programmable Filter and Speaker-Amp of (10) must be powered-up in consideration of PLL
lock time after a sampling frequency is changed.
(2) Set up the path of DAC → SPK-Amp: DACS bit = “0” → “1” (Addr = 02H)
(3) SPK-Amp gain setting: SPKG1-0 bits = “00” → “01” (Addr = 03H)
(4) Set up FRN, FRATT and ADRST1-0 bits (Addr = 09H)
(5) Set up ALC mode (Addr = 0AH, 0BH)
(6) Set up REF value of ALC (Addr = 0CH)
(7) Set up IVOL value of ALC operation start (Addr = 0DH)
(8) Set up the output digital volume. (Addr = 10H)
(9) Set up Programmable Filter Path: PFDAC1-0 bits=“01”, PFSDO=ADCPF bits=“0” (Addr = 18H)
(10) Power up DAC and Programmable Filter: PMDAC=PMPFIL bits=“0”→“1” (Addr = 00H)
(11) Power up Speaker-Amp: PMSL bit=“0”→“1” (Addr = 01H)
(12) Exit the power-save mode of Speaker-Amp: SLPSN bit = “0” → “1” (Addr = 02H)
(13) Enter Speaker-Amp Power Save Mode: SLPSN bit = “1” → “0” (Addr = 02H)
(14) Disable the path of DAC → SPK-Amp: DACS bit = “1” → “0” (Addr = 02H)
(15) Power down Speaker-Amp: PMSL bit= “1”→“0” (Addr =01H)
(16) Power down DAC and Programmable Filter: PMDAC=PMPFIL bits= “1”→“0” (Addr = 00H)
015010680-E-00
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2015/09