AK4637 Datasheet, PDF (29/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to the
MCKI pin, the internal PLL circuit generates BICK and FCK clocks. When the state of AK4637 is ADC
power-down or Loopback mode, the output of BICK, FCK and SDTO pins can be stopped by CKOFF bit.
When CKOFF bit = “1”, BICK, FCK and SDTO pins output “L”. The sampling frequency is selected by
FS3-0 bits as defined in Table 7. The BICK output frequency is selected between 16fs, 32fs or 64fs, by
BCKO bit (Table 9).
AK4637
11.2896MHz, 12MHz, 12.288MHz,
13.5MHz, 24MHz, 27MHz
DSP or P
MCKI
BICK
FCK
SDTO
SDTI
16fs, 32fs, 64fs
1fs
BCLK
FCK
SDTI
SDTO
Figure 21. PLL Master Mode
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency (Note 29)
1
0
0
0
1
8kHz mode
2
0
0
1
0
11.025kHz mode
3
0
0
1
1
12kHz mode
5
0
1
0
1
16kHz mode
6
0
1
1
0
22.05kHz mode
7
0
1
1
1
24kHz mode
9
1
0
0
1
32kHz mode
10
1
0
1
0
44.1kHz mode
11
1
0
1
1
48kHz mode
(default)
Others
Others
N/A
Table 7. Setting of Sampling Frequency (Reference Clock = MCKI pin) (N/A: Not Available)
Note 29. When the MCKI pin is the PLL reference clock input, the sampling frequency generated by PLL
differs from the sampling frequency of mode name in some combinations of MCKI
frequency(PLL3-0 bits) and sampling frequency (FS3-0 bits). Refer to Table 8 for the details of
sampling frequency. In master mode, FCK and BICK output frequency correspond to sampling
frequencies shown in Table 8.
015010680-E-00
- 29 -
2015/09