AK4637 Datasheet, PDF (84/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
11. Control Sequence
■ Clock Set Up
When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied. Turn off the power
management bits first when switching the master clock. The power management bits should be turned on
after the master clock is stabilized.
1. PLL Master Mode
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D2)
MCKI pin
M/S bit
(Addr:01H, D3)
BICK pin
FCK pin
(1)
(2) (3)
>2.0ms
(4)
Input
Example:
Audio I/F Format: I2S Compatible (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
Sampling Frequency: 48kHz
(1) Power Supply & PDN pin = “L”  “H”
(2)Dummy Command
Addr:01H, Data:08H
Addr:05H, Data:62H
Addr:06H, Data:0BH
Addr:07H, Data:03H
(3)Addr:00H, Data:40H
5ms (max)
(5)
Output
Figure 66. Clock Set Up Sequence (1)
(4)Addr:01H, Data:0CH
BICK and FCK output
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 200ns or more is needed to reset the AK4637.
(2) After Dummy Command (Addr:00H, Data:00H) input, M/S, PLL3-0, BCKO1-0, FS3-0, MSBS,
BCKP and DIF1-0 bits must be set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time
is 2.0ms (max) when the capacitance of an external capacitor for the VCOM is 2.2μF (AVDD ≤
3.6V), 4.7μF(AVDD > 3.6V) and the REGFIL pin is 2.2μF.
(4) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source,
and PLL lock time is 5ms (max)
(5) The AK4637 starts to output the BICK and FCK clocks after the PLL became stable. Then
normal operation starts.
015010680-E-00
- 84 -
2015/09