AK4637 Datasheet, PDF (50/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block. When ADCPF bit is “1”, the ALC circuit
operates for recording path, and the ALC circuit operates for playback path when ADCPF bit is “0”. ALC
bit controls ON/OFF of ALC operation.
The ALC block consists of these blocks shown below. The ALC limiter detection level is monitored at the
level detection2 block after EQ block. The level detection1 block also monitors clipping detection level
(+0.53dBFS).
Input
ALC
Control
Volume
Level
Detection2
EQ
Level
Detection1
Output
Figure 45. ALC Block
The polar (fc₁) and the zero point (fs₂) frequencies of EQ block are set by EQFC1-0 bits. Set EQFC bits
according to the sampling frequency. When ALCEQ bit is OFF (ALCEQN bit = “1”), the level detection is
not executed on this block.
EQFC1-0
bits
00
01
10
11
Sampling Frequency
Polar Frequency
Zero-point Frequency
Range
(fc₁)
(fc₂)
8kHz ≤ fs ≤ 12kHz 150Hz @ fs=12kHz 100Hz @ fs=12kHz
12kHz < fs ≤ 24kHz 150Hz @ fs=24kHz 100Hz @ fs=24kHz
24kHz < fs ≤ 48kHz 150Hz @ fs=48kHz 100Hz @ fs=48kHz
N/A
Table 28. ALCEQ Frequency Setting (EQFC1-0 bits; N/A: Not available)
(default)
[ALCEQ: First order zero pole high pass filter]
Gain
[dB]
0dB
-3.5dB
100Hz
(fc₂)
150Hz
(fc₁)
Frequency
[Hz]
Note 35. Black: Diagrammatic Line, Red: Actual Curve
Figure 46. ALCEQ Frequency Response (fs = 48kHz)
015010680-E-00
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2015/09