AK4637 Datasheet, PDF (65/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
■ Serial Control Interface
The AK4637 supports the fast-mode I²C Bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins
must be connected to a voltage in the range from TVDD or more to 6V or less.
1. WRITE Operations
Figure 56 shows the data transfer sequence for the I²C Bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 62). After the START condition, a slave address is sent. This address is seven bits of the
slave address are fixed as “0010010” and the next bit is a data direction bit (R/W) (Figure 57). If the slave
address matches that of the AK4637, the AK4637 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line
(HIGH) during the acknowledge clock pulse (Figure 63). A R/W bit value of “1” indicates that the read
operation is to be executed, and “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4637. The format is MSB first, and
those most significant 1bit is fixed to zero (Figure 58). The data after the second byte contains control
data. The format is MSB first, 8bits (Figure 59). The AK4637 generates an acknowledge after each byte is
received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 62).
The AK4637 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK4637 generates an acknowledge and awaits the next data. The master can transmit more than one
byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data
packet the internal address counter is incremented by one, and the next data is automatically taken into
the next address. The address counter will “roll over” to 00H and the previous data will be overwritten if
the address exceeds “3FH” prior to generating a stop condition.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 64) except for the
START and STOP conditions.
SDA
S
T
R/W ="0"
A
R
T
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
S
T
O
P
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 56. Data Transfer Sequence at I²C Bus Mode
0
0
1
0
0
1
0
R/W
Figure 57. The First Byte
0
A6
A5
A4
A3
A2
A1
A0
Figure 58. The Second Byte
015010680-E-00
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2015/09