AK4637 Datasheet, PDF (32/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4637 becomes EXT mode. Master clock can be input to the internal ADC
and DAC directly from the MCKI pin without internal PLL circuit operation. This mode is compatible with
I/F of a normal audio CODEC. The external clocks required to operate this mode are MCKI (256fs, 384fs,
512fs or 1024fs), FCK (fs) and BICK (16fs). The master clock (MCKI) must be synchronized with FCK.
The phase between these clocks is not important. The input frequency of MCKI is selected by CM1-0 bits
(Table 11) and the sampling frequency is selected by FS3-2 bits (Table 12).
Mode CM1 bit CM0 bit
MCKI Input
Frequency
Sampling Frequency
Range
0
0
0
256fs
8kHz ≤ fs ≤ 48kHz
(default)
1
0
1
384fs
8kHz ≤ fs ≤ 48kHz
2
1
0
512fs
8kHz ≤ fs ≤ 48kHz
3
1
1
1024fs
8kHz ≤ fs ≤ 24kHz
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
Mode
0
1
2
Others
FS3 bit FS2 bit FS1 bit FS0 bit
Sampling Frequency
0
0
x
x
8kHz ≤ fs ≤ 12kHz
0
1
x
x
12kHz < fs ≤ 24kHz
1
0
x
x
24kHz < fs ≤ 48kHz
Others
N/A
Table 12. Setting of Sampling Frequency (N/A: Not Available)
(default)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to
out-of-band noise. The out-of-band noise can be reduced by using higher frequency of the master clock.
The S/N of the DAC output through SPP/SPN pins is shown in Table 13.
MCKI
S/N (fs=8kHz, 20kHzLPF + A-weighted)
256fs
80dB
384fs
80dB
512fs
93dB
1024fs
96dB
Table 13. Relationship between MCKI and S/N of SPP/SPN pins
AK4637
MCKI
BICK
FCK
SDTO
SDTI
256fs, 384fs,
512fs or 1024fs
 16fs
1fs
DSP or P
MCLK
BCLK
FCK
SDTI
SDTO
Figure 23. EXT Slave Mode
015010680-E-00
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2015/09