AK4637 Datasheet, PDF (27/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
9. Functional Descriptions
■ System Clock
There are the following four clock modes to interface with external devices (Table 2, Table 3).
Mode
PMPLL bit
M/S bit
PLL3-0 bits
PLL Master Mode
1
1
Table 5
PLL Slave Mode
(PLL Reference Clock: BICK pin)
1
0
Table 5
EXT Slave Mode
0
0
X
EXT Master Mode
0
1
X
Table 2. Clock Mode Setting (x: Don’t care)
Figure
Figure 21
Figure 22
Figure 23
Figure 24
Mode
MCKI pin
BICK pin
PLL Master Mode
Input Frequency of Table 5
Output
(Selected by PLL3-0 bits) (Selected by BCKO bit)
PLL Slave Mode
(PLL Reference Clock: BICK pin)
EXT Slave Mode
EXT Master Mode
GND
Input
(Selected by PLL3-0 bits)
Input Frequency of Table 11
Input
(Selected by CM1-0 bits)
( 32fs)
Input Frequency of Table 14
Output
(Selected by CM1-0 bits) (Selected by BCKO bit)
Table 3. Clock Pins States in Clock Mode
FCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave
mode. When the AK4637 is in power-down mode (PDN pin = “L”) and when exits reset state, the AK4637
is in slave mode. After exiting reset state, the AK4637 goes to master mode by changing M/S bit to “1”.
When the AK4637 is in master mode, the FCK and BICK pins are a floating state until M/S bit becomes
“1”. The FCK and BICK pins of the AK4637 must be pulled-down or pulled-up by a resistor (about 100k)
externally to avoid the floating state.
M/S bit
Mode
0
Slave Mode (default)
1
Master Mode
Table 4. Select Master/Slave Mode
015010680-E-00
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2015/09