AK4637 Datasheet, PDF (59/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC - SPK-AMP

[AK4637]
■ BEEP Input
When BEEPS bit is set to “1” during PMBP = PMSL = SPLSN bits = “1”, the input signal from the BEEP
pin is output to the speaker amplifier (LOSEL bit = “0”) or mono line output (LOSEL bit = “1”). When BEEP
input is performed, MDIF bit must be set to “0”. BPLVL3-0 bits set the gain of BEEP-Amp. The total gain is
defined according to SPKG1-0 bits setting when speaker amplifier is performed, and LVCM1-0 bits when
mono line output is performed.
Input BEEP gain is controlled by BPLVL3-0 bits (Table 45).
BPLVL3 bit BPLVL2 bit BPLVL1 bit BPLVL0 bit BEEP Gain
0
0
0
0
0dB (default)
0
0
0
1
6dB
0
0
1
0
12dB
0
0
1
1
18dB
0
1
0
0
24dB
0
1
0
1
30dB
0
1
1
0
33dB
0
1
1
1
36dB
1
0
0
0
39dB
1
0
0
1
42dB
Others
N/A
Table 45. BEEP Output Gain Setting (N/A: Not available)
BPVCM bit set the common voltage of BEEP input amplifier (Table 46).
BPVCM bit BEEP-Amp Common Voltage (typ)
0
1.15V
(default)
1
1.65V (Note 14, Note 36)
Note 14. The maximum value is the smaller one of AVDD Vpp or 3.3Vpp when BPVCM bit = “1”. However,
a click noise may occur when the amplitude after BEEP-Amp is 0.5Vpp or more. (Set by
BPLVL3-0 bits)
Note 36. When the BEEP signal is output to the speaker amplifier and BPVCM bit = “1”, AVDD must be
supplied 2.8V or more.
Table 46. Common Potential Setting of BEEP-Amp
BEEP/IN- pin
To MIC-Amp
BPLVL3-0 bits
“1”
“0”
MDIF bit
BEEPS bit
BEEP-Amp
Figure 49. Block Diagram of BEEP pin
To Speaker-Amp
or Lineout-Amp
015010680-E-00
- 59 -
2015/09