AK4562 Datasheet, PDF (9/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
SWITCHING CHARACTERISTICS
(Ta=-20 ∼ 70°C; VA, VD=2.2 ∼ 3.0V, VT=1.8 ∼ 3.0V; C_L=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock (MCLK)
256fs: Frequency
Pulse Width Low
Pulse Width High
384fs: Frequency
Pulse Width Low
Pulse Width High
Channel Clock (LRCK) Frequency
Duty Cycle
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
2.048
28
28
3.072
23
23
8
45
11.2896
16.9344
44.1
Audio Interface Timing
BCLK Period
BCLK Pulse Width Low
Pulse Width High
BCLK “↓” to LRCK
LRCK Edge to SDTO (MSB)
BCLK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tBLK
tBLKL
tBLKH
tBLR
tDLR
tDSS
tSDH
tSDS
312.5
130
130
-tBLKH+50
50
50
Control Interface Timing (AKM)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDATA Setup Time
CDATA Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
200
tCCKL
80
tCCKH
80
tCDS
50
tCDH
50
tCSW
150
tCSS
50
tCSH
50
Control Interface Timing (SSB)
SCK Period
SCLK Pulse Width Low
Pulse Width High
SSI Setup Time
SSI Hold Time
tSCK
250
tSCKL
100
tSCKH
100
tSIS
50
tSIH
50
Reset / Calibration Timing
PDN Pulse Width
tPW
150
PDN “↑” to SDTO
(Note 14)
tPWV
4128
max
12.8
19.2
50
55
tBLKL-50
80
80
Units
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note : 14. These cycles are the numbers of LRCK rising from PDN pin rising.
MS0031-E-00
-9-
2000/05