AK4562 Datasheet, PDF (12/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
OPERATION OVERVIEW
n System Clock
The clocks that are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs∼). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care. The frequency of MCLK can be input 256fs or
384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC and DAC are in operation. If
these clocks are not provided, the AK4562 may draw excess current and it is not possible to operate properly because
utilizes dynamic refreshed internally. If the external clocks are not present, the AK4562 should be in the power-down
mode.
n Audio Data I/F Format
Using SDTO, SDTI, BCLK and LRCK pins are connected to external system. Audio data format has four kinds of mode,
the data format is MSB-first, 2’s compliment. Setting by DIF0-1 bit. The default value is DIF0 = DIF1 = “0”.
No. DIF1 bit DIF0 bit SDTO (ADC)
SDTI (DAC)
0
0
0
20bit MSB justified 20bit LSB justified
1
0
1
20bit MSB justified 16bit LSB justified
2
1
3
1
0
20bit MSB justified 24bit LSB justified
1
I²S Compatible
I²S Compatible
Table 1. Audio Data Format
LRCK
Lch: “H”, Rch: “L”
Lch: “H”, Rch: “L”
Lch: “H”, Rch: “L”
Lch: “L”, Rch: “H”
BCLK
≥ 40fs
≥ 32fs
≥ 48fs
≥ 40fs
LRCK
01 2
BCLK(64fs)
12 13 14
20 21
SDTO(o)
19 18
876
0
31 0 1 2
12 13 14
20 21
19 18
876
0
31 0 1
19
SDTI(i)
Don’t Care 19 18
12 11
1 0 Don’t Care
19:MSB, 0:LSB
Lch Data
Figure 7. Audio Data Format (No.0)
19 18
12 11
Rch Data
10
LRCK
01 2
BCLK(64fs)
15 16 17
20 21
SDTO(o)
19 18
54 3
0
31 0 1 2
15 16 17
20 21
19 18
5 43
0
31 0 1
19
SDTI(i)
Don’t Care 15
12 11
1 0 Don’t Care
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
Figure 8. Audio Data Format (No.1)
15
12 11
Rch Data
10
MS0031-E-00
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2000/05