AK4562 Datasheet, PDF (14/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
Power Supply
PDN pin
PDN pin may be “L” at power-up.
ADC Internal
State
PD
AIN
4128/fs
CAL
GD
Normal
SDTO
DAC Internal
State
SDTI
AOUT1
Control register
“0”data (4)
PD
Normal
(5)
INIT-2
GD (1)
W rite to register
Inhibit-1 Inhibit-2
PM
GD (1)
4128/fs
INIT-1
Normal
GD
(2) _{(3) “0”data}
Idle Noise
PM
(1)
Normal
GD (1)
“0”data
(5)
GD (1)
Normal
Normal
External clocks
(6)
(6)
The clocks may be stopped.
Figure 11. Power up / Power down Timing Example
• PD:
• PM:
• CAL:
• INIT-1:
• INIT-2:
• Inhibit-1:
• Inhibit-2:
Power-down state. ADC is output “0”, analog output of DAC and OPGA goes floating.
Power-down state by Power Management bit. ADC is output “0”, analog output of DAC goes floating.
During offset calibration cycle. IPGA and OPGA are set MUTE state.
Initialize cycle of ADC. Offset calibration is not executed.
Initializing all control registers.
Inhibits writing to all control registers.
Enable writing to control registers except address 01H.
Note: See “Register Definitions” about the condition of each register.
(1). Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD). Output signal gradually comes to settle to input signal during a group delay.
(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of a
internal ADC.
(3). ADC output is “0” at power down.
(4). This figure shows that MUTE of IPGA is canceled during offset calibration. If MUTE of IPGA is canceled, SDTO
outputs Idle Noise.
(5). Click noise occurs at the “↑↓” of PDN signal. Please mute the analog output external if the click noise influences
system application.
(6). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK4562 should be in the power down
(PDN pin = “L” or PM2-1 bit = “0”) mode.
MS0031-E-00
- 14 -
2000/05