AK4562 Datasheet, PDF (24/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
• Write command
When D/C bit is “1”, 8 bit data after information bits indicates a command.
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13
01 2
SSI
ST WR C D0 D1 D2 D3 D4 D5 D6 D7
D0-D3:
D0-D7:
Device Code
Instruction Code
ST WR D
Internal W rite Tim ing
Figure 19. Write Command Timing
• Device code
D0-3 bits are the device code, the bus can be connected to maximum 16 devices, however, and the device code
is fixed to 05H in the AK4562.
• Instruction code
The following instruction is set by D4-D7 bits.
Instruction Code
D4 D5 D6 D7
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
-----
0
1
1
1
1
1
1
1
Command
RESET
ADRSL
NOP
AINC
ADEC
AHOLD
Function
Only the contents of control register are reset.
When the next data is data write, the address is sent.
If not so, this command is invalidated.
Invalidity
Auto increment mode of address
Holds this state until sending the next ADEC and AHOLD.
Auto decrement mode of address
Holds this state until sending the next AINC and AHOLD.
Fixed mode of address
Holds this state until sending the next AINC and ADEC.
NOP
Invalidity
RESET
Only the contents of control register are reset.
Table 6. SSB Instruction
SSB I/F becomes disable by PDN = “L”, it is set to address = “00H”, AHOLD mode. Therefore, after exiting
PDN = “L” at power-on, SSB I/F is enabled by writing command (including NOP) of a appointed device code
and accepts data WRITE ever since.
• Data write
When D/C bit is “0”, 8 bit data after the information bits indicates Data. If ADRSL command is sent just before
the data is written as the address. The control data is sent in the other case.
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13
01 2
SSI
ST WR D D0 D1 D2 D3 D4 D5 D6 D7
D0-D7: Address or Control Data
ST WR D
Internal Write Timing
Figure 20. Data Write Timing
MS0031-E-00
- 24 -
2000/05