AK4562 Datasheet, PDF (15/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
n Timing of Control Register
• AKM mode
AKM mode is the data in I/F with 3-wire serial control, these data are included by Op-code (3bit), Address
(LSB-first, 5bit) and Control data (LSB-first, 8bit). A side of transmitted data is output to each bit by “↓” of
CCLK, a side of receiving data is input by “↑” of CCLK. Writing of data becomes effective by “↑” of CSN. CSN
should be held to “H” at no access.
Address except 00H ∼ 04H inhibits control of writing. And CCLK always need 16 edges of “↑” during CSN =
“L”.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
op0 op1 op2 A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7
“*” “*” “1”
op0-op2: Op code (Fixed to “**1:WRITE”)
A0-A4: Register Address
D0-D7: Control data
Figure 12. Control Data Timing (AKM)
• SSB mode
SSB mode is the data in I/F with 2-wire serial interface, these data are included by information bit (3bit) and data
bit (LSB-first, 8bit). Serial clock (SCK) is burst-transmitted, not continuous receiving data. Transmitter outputs
each bit by “↑” of SCK, receiver latches the bit when transmitting the data is input by “↓” of SCK. Writing of data
and command becomes effective by next “↑” of SCK after taking in the last data bit (D7).
Address except 00H ∼ 04H inhibits control of writing.
SCK
0 1 2 3 4 5 6 7 8 9 10
SSI
ST R/W D/C D0 D1 D2 D3 D4 D5 D6 D7
ST:
R/W:
D/C:
D0-D7:
Start bit (1: Start)
Read/Write bit (Fixed to “1: Write”)
Data/Command bit (0: Data, 1: Command)
Address or Control Data
Command Write
Data Write
ST WR C D0 D1 D2 D3 D4 D5 D6 D7
“1” “1” “1” D0-D3: Device Code, D4-D7: Instruction Code
ST WR D D0 D1 D2 D3 D4 D5 D6 D7
“1” “1” “0” D0-D7: Address or Control Data
Figure 13. Control Data Timing (SSB)
MS0031-E-00
- 15 -
2000/05