AK4562 Datasheet, PDF (22/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
n Detail of functions
(1) Input Analog PGA with Zero Crossing Detection
Zero crossing is detected on L/R channels independently. If zero crossing is not detected, IPGA value changes by
timeout. Timeout cycle can be set by ZTM1-0 bit. For example, when ZTM1-0 is “11”, timeout cycle is 2048/fs =
46.4ms (@fs=44.kHz). Zero crossing detection function can be controlled by ON/OFF of ZEIP bit. If ZEIP is OFF,
gain level changes immediately by writing IPGA value.
Offset calibration starts by PDN pin “L” to “H”. IPGA is set MUTE during offset calibration and after offset
calibration.
(2) Monaural Mixing
Lch ^ADC
HPF
SW1
Lch
Rch
ADC
HPF
+
x 0.5
SW2
Rch
Figure 16. Monaural Mixing
Mode
Stereo Recording
Monaural Recording
Stereo Input
Monaural Recording
Lch Input only
Monaural Recording
Rch Input only
SW1
Lch
(L+R)/2
SW2
Rch
(L+R)/2
MONO1
0
0
Lch
Lch
1
Rch
Rch
1
Table 5. Monaural Mode Setting
(3) De-emphasis
Include digital de-emphasis filter circuit with tc=50/15us.
MONO0
0
1
0
1
MS0031-E-00
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2000/05