AK4562 Datasheet, PDF (20/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
• About zero crossing operation
Comparator for zero crossing detection in the AK4562 has offset. Therefore, it is a possible that IPGA (OPGA)
value is changed by zero crossing timeout as zero crossing detection does not occur by a little offset of
comparator.
For example, when Lch and Rch are in the state of IPGA (OPGA) = 30H, both channels are set to IPGA (OPGA)
= 31H. And then the only Lch completed zero crossing, Rch is waiting for zero crossing detection, zero crossing
counter is reset when IPGA (OPGA) is newly written 32H, zero crossing operation starts toward IPGA (OPGA) =
32H in state Lch = 31H, Rch = 30H. Internal IPGA (OPGA) value in the AK4562 has the registers of L/R channels
independently, according to change IPGA (OPGA) value independently, IPGA (OPGA) value of L/R channels
may become a difference in level.
Therefore, if IPGA (OPGA) is written before zero crossing detection on zero crossing timeout, IPGA (OPGA) is
keeping the same value. When IPGA (OPGA) is finished by normal zero crossing timeout on IPGA (OPGA) value
of L/R channels does not give a difference in level, the change of IPGA (OPGA) should be written after zero
crossing timeout cycle and over.
Internal zero crossing
operation completion flag
Lch Internal IPGA _30H
31H
32H
(OPGA)
Zero crossing
Rch Internal IPGA 30H
30H
32H
(OPGA)
IPGA Register 30H
31H
32H
(OPGA)
WR[IPGA(OPGA)=31H]
Reset zero crossing timer
WR[IPGA(OPGA)=32H]
Reset zero crossing timer
Figure 15. About Zero Crossing Operation
MS0031-E-00
- 20 -
2000/05