AK4562 Datasheet, PDF (21/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
Output Analog PGA Control
Addr
04H
Register Name
Output Analog PGA Control
RESET
D7
ZEOP
0
D6
OPGA6
D5
OPGA5
D4
D3
D2
OPGA4 OPGA3 OPGA2
00H (MUTE)
D1
OPGA1
D0
OPGA0
ZEOP:
Select OPGA zero crossing operation (0: Disable, 1: Enable)
Writing to OPGA value at ZEOP = “1”, OPGA value of L/R channels changes by zero crossing
detection or timeout independently.
Timeout cycle can be set by ZTM1-0 bit.
When ZTM1-0 is “11”, timeout cycle is 2048/fs = 46.4ms (@fs=44.kHz).
When ZEOP is “0”, OPGA changes immediately.
OPGA6-0: Output Analog PGA. 58 levels. 00H=MUTE.
ON/OFF of zero crossing detection can be controlled by ZEOP bit.
Please do not use 3AH ∼ 7FH.
DATA (D6-0) HEX CODE OPGA (dB) Step
011 1001
39H
+0
011 1000
38H
-1
011 0111
37H
•
•
-2
•
1dB
001 1000
18H
-33
001 0111
17H
-34
001 0110
16H
-36
001 0101
15H
-38
•
•
000 0011
03H
•
2dB
-74
000 0010
02H
-76
000 0001
01H
-78
000 0000
00H
MUTE
Table 4. Output Gain Setting
Level
35
22
1
MS0031-E-00
- 21 -
2000/05