AK4562 Datasheet, PDF (16/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
n Register Map
Addr
00H
01H
02H
03H
04H
Register Name
Input Select
Mode Control 1
Mode Control 2
Input Analog PGA Control
Output Analog PGA Control
D7
0
0
MONO1
ZEIP
ZEOP
D6
0
0
MONO0
IPGA6
OPGA6
D5
0
0
ZTM1
IPGA5
OPGA5
D4
0
0
ZTM0
IPGA4
OPGA4
D3
RIN2
PM3
DEM1
IPGA3
OPGA3
D2
RIN1
PM2
DEM0
IPGA2
OPGA2
D1
LIN2
PM1
DIF1
IPGA1
OPGA1
D0
LIN1
PM0
DIF0
IPGA0
OPGA0
All registers are reset at PDN = “L”, then inhibits writing to all registers.
n Register Definition
Input Select
Addr
00H
Register Name
Input Select
RESET
D7
D6
D5
0
0
0
0
0
0
LIN2-1: Select ON/OFF of Lch input. (0: OFF, 1: ON)
RIN2-1: Select ON/OFF of Rch input. (0: OFF, 1: ON)
D4
D3
D2
D1
D0
0
RIN2
RIN1
LIN2
LIN1
0
0
1
0
1
Mode Control 1
Addr
01H
Register Name
Mode Control 1
RESET
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
PM3
PM2
PM1
PM0
0
0
0
0
1
1
1
1
PM3-0:
Power Management (0: Power down, 1: Power up)
PM0:Power control of IMIX and IPGA
PM1:Power control of ADC
PM2:Power control of DAC
PM3:Power control of OPGA
PM3-0 can be partly powered-down by ON/OFF of PM3-0. When PDN pin goes “L”, all circuit in the AK4562 can
be powered-down in no relation to PM3-0. When PM3-0 goes all “0”, all circuit in the AK4562 can be also
powered-down. However, the contents of control registers are held.
In case of PM1 = “1” or PM2 = “1”, MCLK is not stopped.
In case of PM0 = “1” or PM3 = “1”, the powered-up circuit does not need MCLK. However, zero crossing detection
can not operate in this case.
MS0031-E-00
- 16 -
2000/05