AK4562 Datasheet, PDF (13/29 Pages) Asahi Kasei Microsystems – LOW POWER 20BIT CODEC WITH PGA

ASAHI KASEI
[AK4562]
LRCK
01 2
BCLK(64fs)
8 9 10
20 21
SDTO(o)
19 18
12 11 10
0
31 0 1 2
8 9 10
20 21
19 18
12 11 10
0
31 0 1
19
SDTI(i)
Don’t Care 23 22
12 11
1 0 Don’t Care
SDTO-19:MSB, 0:LSB; SDTI-23:MSB, 0:LSB
Lch Data
Figure 9. Audio Data Format (No.2)
23 22
12 11
Rch Data
10
LRCK
0 1 2 3 19 20 21 22 23 24 25
BCLK(64fs)
SDTO(o)
19 18
10
0 1 2 3 19 20 21 22 23 24 25
19 18
10
01
SDTI(i)
19 18
10
Don’t Care
19 18
19:MSB, 0:LSB
Lch Data
Figure 10. Audio Data Format (No.3)
10
Don’t Care
Rch Data
n Digital High Pass Filter
The AK4562 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC and IPGA. The cut-off frequency of the
HPF is 3.4Hz at fs=44.1kHz. It also scales with the sampling frequency (fs).
n System Reset & Offset Calibration
The AK4562 should be reset once by bringing PDN pin “L” after power-up. The control register values are initialized by
PDN “L”.
Offset calibration starts by PDN pin “L” to “H”. It takes 4128/fs to offset calibration cycle. During offset calibration, the
ADC digital data outputs of both channels are forced to a 2’s compliment “0”. Output data of settles data equivalent for
analog input signal after offset calibration. This cycle is not for DAC. IPGA and OPGA are set MUTE during offset
calibration and after offset calibration.
As a normal offset calibration may not be executed, nothing write at address 01H during offset calibration.
When offset calibration is executed once, the calibration memory is held even if each block is powered down (PM0 = “0”
or PM3 = “0”) by power management bits.
MS0031-E-00
- 13 -
2000/05