AK4118A Datasheet, PDF (9/56 Pages) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio I/F Transceiver

SWITCHING CHARACTERISTICS
(Ta=25°C; DVDD=AVDD2.7~3.6V, TVDD=2.7~5.5V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Crystal Resonator Frequency
fXTAL 11.2896
External Clock
Frequency (Note 7) fECLK 8.192
Duty
dECLK
40
50
MCKO1 Output
Frequency
Duty
fMCK1 4.096
dMCK1
40
50
MCKO2 Output
Frequency
Duty
fMCK2 2.048
dMCK2
40
50
PLL Clock Recover Frequency (RX0-7)
Fpll
8
-
LRCK Frequency
Duty Cycle
fs
8
dLCK
45
Audio Interface Timing
Slave Mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
LRCK to SDTO (MSB)
BICK “↓” to SDTO
DAUX Hold Time
DAUX Setup Time
tBCK
80
tBCKL
30
tBCKH
30
(Note 8)
tLRB
20
(Note 8)
tBLR
20
tLRM
tBSD
tDXH
20
tDXS
20
Master Mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
DAUX Hold Time
DAUX Setup Time
fBCK
64fs
dBCK
50
tMBLR
-20
tBSD
-15
tDXH
20
tDXS
20
Control Interface Timing (4-wire serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCCK
200
tCCKL
80
tCCKH
80
tCDS
50
tCDH
50
tCSW
150
tCSS
50
tCSH
50
tDCD
tCCZ
Note 7. When fECLK=8.192MHz, sampling frequency detect function (page16) is disable.
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
[AK4118A]
max
24.576
24.576
60
24.576
60
24.576
60
192
192
55
Units
MHz
MHz
%
MHz
%
MHz
%
kHz
kHz
%
ns
ns
ns
ns
ns
30
ns
30
ns
ns
ns
Hz
%
20
ns
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
ns
70
ns
MS1130-E-02
-9-
2009/12