AK4118A Datasheet, PDF (38/56 Pages) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio I/F Transceiver

[AK4118A]
(2)-2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4118A.
After receipt the start condition and the first byte, the AK4118A generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of the AK4118A. The format is MSB first,
and those most significant 3-bits are “Don’t care”.
0
0
A5
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 39. The Second Byte
After receipt the second byte, the AK4118A generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 40. Byte structure after the second byte
The AK4118A is capable of more than one byte write operation in one sequence.
After receipt of the third byte, the AK4118A generates an acknowledge, and awaits the next data again. The master can
transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll over” to
00H and the previous data will be overwritten.
SDA
S
T
A _Slave
R _Address
T
Register
Address(n)
Data(n)
Data(n+1)
S
A
A
A
A
C
C
C
C
K
K
K
K
Figure 41. WRITE Operation
S
T
Data(n+x) _O
P
P
MS1130-E-02
- 38 -
2009/12