AK4118A Datasheet, PDF (28/56 Pages) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio I/F Transceiver

[AK4118A]
1. Parallel control mode
In parallel control mode, the INT0 pin outputs the ORed signal between UNLCK and PAR. The INT1 pin outputs the
ORed signal between AUTO and AUDION. Once the INT0 pin goes to “H”, it maintains “H” for 1024/fs cycles after the
all error events are removed. Table 15 shows the state of each output pins when the INT0/1 pin is “H”.
Event
Pin
UNLCK PAR AUTO AUDION INT0 INT1
SDTO
V
1
x
x
0
1
x
x
x
H
L
L
Note 14 Previous Data Output
0
0
x
x
L
Output
Output
x
x
1
x
x
x
x
1
Note 15
H
Note 16
Note 17
x
x
0
0
L
Note 14. The INT1 pin outputs “L” or “H” in accordance with the ORed signal between AUTO and AUDION.
Note 15. The INT0 pin outputs “L” or “H” in accordance with the ORed signal between UNLCK and PAR.
Note 16. The SDTO pin outputs “L”, “Previous Data” or “Normal Data” in accordance with the ORed signal between
UNLCK and PAR.
Note 17. The VIN pin outputs “L” or “Normal operation” in accordance with the ORed signal between PAR and
UNCLK.
Table 15. Error Handling in parallel control mode (x: Don’t care)
2. Serial control mode
In serial control mode, the INT1 and INT0 pins output an ORed signal based on the above nine interrupt events. When
masked, the interrupt event does not affect the operation of the INT1-0 pins (the masks do not affect the registers in 07H
and DAT bit). Once the INT0 pin goes to “H”, it remains “H” for 1024/fs (this value can be changed with the EFH1-0
bits) after all events not masked by mask bits are cleared. The INT1 pin immediately goes to “L” when those events are
cleared.
UNLCK, PAR, AUTO, AUDION and V bits in Address=07H indicate the interrupt status events above in real time. Once
QINT, CINT and DAT bits goes to “1”, it stays “1” until the register is read.
When the AK4118A loses lock, the channel status bit, user bit, Pc and Pd are initialized. In this initial state, The INT0 pin
outputs the ORed signal between UNLCK and PAR bits. The INT1 pin outputs the ORed signal between AUTO and
AUDION bits.
UNLCK
1
0
x
Event
Pin
PAR
Others
SDTO
V
x
x
L
L
1
x
Previous Data Output
x
x
Output
Output
Table 16. Error Handling in serial control mode (x: Don’t care)
TX
Output
Output
Output
MS1130-E-02
- 28 -
2009/12