AK4118A Datasheet, PDF(37/56 Page) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio I/F Transceiver

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AK4118A Datasheet, PDF (37/56 Pages) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio I/F Transceiver

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[AK4118A]

(2)-1-3. Acknowledge

An external device that is sending data to the AK4118A releases the SDA line (âHâ) after receiving one-byte of data. An

external device that receives data from the AK4118A then sets the SDA line to âLâ at the next clock. This operation is

called âacknowledgementâ, and it enables verification that the data transfer has been properly executed. The AK4118A

generates an acknowledgement upon receipt of Start condition and Slave address. For a write instruction, an

acknowledgement is generated whenever receipt of each byte is completed. For a read instruction, succeeded by

generation of an acknowledgement, the AK4118A releases the SDA line after outputting data at the designated address,

and it monitors the SDA line condition. When the Master side generates an acknowledgement without sending a Stop

condition, the AK4118A outputs data at the next address location. When no acknowledgement is generated, the AK4118A

ends data output (not acknowledged).

Clock pulse

for acknowledge

SCL FROM

MASTER

DATA

OUTPUT BY

TRANSMITTER

DATA

OUTPUT BY

RECEIVER

START

CONDITION

Figure 37. Acknowledge on the I2C-bus

not acknowledge

acknowledge

(2)-1-4. The First Byte

The First Byte which includes the Slave-address is input after the Start condition is set, and a target IC device that will be

accessed on the bus is selected by the Slave-address. The Slave-address is configured with the upper 7-bits. Data of the

upper 5-bits is â00100â. The next 2 bits are address bits that select the desired IC which are set by the CAD1 and CAD0

pins. When the Slave-address is inputted, an external device that has the identical device address generates an

acknowledgement and instructions are then executed. The 8th bit of the First Byte (lowest bit) is allocated as the R/W Bit.

When the R/W Bit is â1â, the read instruction is executed, and when it is â0â, the write instruction is executed.

0 CAD1 CAD0 R/W

(Those CAD1/0 should match with CAD1/0 pins.)

Figure 38. The First Byte

MS1130-E-02

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2009/12

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