AK4118A Datasheet, PDF (15/56 Pages) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio I/F Transceiver

[AK4118A]
OPERATION OVERVIEW
■ Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The AK4118A has a Non-PCM steam auto-detection function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes “1”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO bit “1”. Once the AUTO is set
“1”, it will remain “1” until 4096 frames pass through the chip without additional sync pattern being detected. When
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers. The
AK4118A also has the DTS-CD bitstream auto-detection function. When AK4118A detects DTS-CD bitstreams, DTSCD
bit goes to “1”. When the next sync code does not come within 4096 flames, DTSCD bit goes to “0” until when
AK4118A detects the stream again. The AK4118A detects 14bit Sync Word and 16bit Sync Word of DTS-CD bitstream.
In Serial control mode this detect function can be ON/OFF by DTS14 bit and DTS16 bit.
■ 192kHz Clock Recovery
The integrated low jitter PLL has a wide lock range from 8kHz to 192kHz and the lock time is dependent on the sampling
frequency and FAST bit setting (Table 1). FAST bit is useful at lower sampling frequency and is fixed to “1” in parallel
control mode. In serial control mode, the AK4118A has a sampling frequency detection function (8kHz, 11.025kHz,
16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) that uses either a clock
comparison against the X’tal oscillator or the channel status information from the setting of XTL1-0 bits. In parallel
control mode, the sampling frequency is detected by using the reference frequency, 24.576MHz. When the sampling
frequency is more than 64kHz, the FS96 pin goes to “H”. When the sampling frequency is less than 54kHz, the FS96 pin
goes to “L”. The PLL loses lock when the received sync interval is incorrect.
FAST bit PLL Lock Time
0
≤ (15 ms + 384/fs) (default)
1
≤ (15 ms + 1/fs)
Table 1. PLL Lock Time (fs: Sampling Frequency)
■ Master Clock
The AK4118A has two clock outputs, MCKO1 and MCKO2. The MCKO2 pin output mode is selected by XMCK bit.
1) XMCK bit = “0”
The AK4118A has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 and MCKO2) are set by OCKS0 and
OCKS1 as shown in Table 2. The 512fs clock will not output when 96kHz and 192kHz. The 256fs clock will not output
when 192kHz. The MCKO2 pin outputs “L” when PLL is the clock source.
No. OCKS1 OCKS0 MCKO1 MCKO2
X’tal
fs (max)
0
0
0
256fs
“L”
256fs
96 kHz
1
0
1
256fs
“L”
256fs
96 kHz
2
1
0
512fs
“L”
512fs
48 kHz
3
1
1
128fs
“L”
128fs
192 kHz
When CM1-0 bits = “00” or “10” and UNLOCK bit= “0”
Table 2. Master Clock Frequency Select (Stereo mode)
(default)
MS1130-E-02
- 15 -
2009/12