AK4563A Datasheet, PDF (8/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
SWITCHING CHARASTERISTICS
(Ta=25°C; VA, VD=2.3 ∼ 3.0V, VT=1.5 ∼ 3.0V; C_L=20pF)
Parameter
Symbol
min
Control Clock Frequency
Master Clock(MCLK) 256fs: Frequency
fCLK
2.048
Pulse Width Low
tCLKL
28
Pulse Width High
tCLKH
28
384fs: Frequency
fCLK
3.072
Pulse Width Low
tCLKL
23
Pulse Width High
tCLKH
23
Channel Selection Clock (LRCK) frequency
fs
8
Duty
45
Audio Interface Timing
BCLK Period
tBLK
312.5
BCLK Pulse Width Low
tBLKL
130
Pulse Width High
tBLKH
130
BCLK “↓” to LRCK
tBLR
-tBLKH+50
LRCK to SDTO(MSB) (Except IIS mode)
tDLR
BCLK “↓” to SDTO
tDSS
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High 1
Pulse Width High 2
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Output Delay Time
CSN “↑” to CDTO(Hi-Z)(Note 13)
tCCK
tCCKL
tCCKH
tCKH2
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200(Note 12)
80
80
80
50
50
150(Note 12)
50(Note 12)
50
Reset/Calibration Timing
PDN Pulse Width
PDN “↑” to SDTO0/SDTO1 valid
tPDW
150
tPDV
typ
max
12.288
12.8
18.432
19.2
48
50
50
55
tBLKL-50
80
80
70
70
4128
Units
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note 12. fs ≥ 22.4kHz.
In the case of fs < 22.4kHz, these three parameters must meet a relationship of
(tCSW + tCSS + 6 × tCCK) > 1/(32 × fs) in addition to these specifications. For example, when tCCK=200ns
and tCSS=50ns at fs=8kHz, tCSW(min) is 2657ns. When tCSW=150ns and tCSS=50ns fs=8kHz, tCCK(min) is
618ns.
When 08H or 09H address is read and fs < 39.1kHz, tCCK must meet a relationship tCCK > 1/(128 × fs) in
addition to these specifications. For example, when fs=8kHz, tCCK(min) is 977ns.
Note 13. R_L=1kΩ/10% Change (Pulled-up operates for VT.)
MS0067-E-02
-8-
2004/12