AK4563A Datasheet, PDF (27/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
„ Operation of IPGA
[Reading operation]
When the IPGA value is read by µP, the IPGA value is the written value finally. Therefore, the actual value may differ
to the IPGA value which is read by µP.
[Writing operation at ALC Enable]
During the ALC operation including the FADEIN/OUT operation, if the IPGA value is written by uP, the IPGA value
does not reflect the present value.
[Writing operation at ALC Disable]
The zero crossing detection of IPGA is done to L/R channels independently. Zero crossing timeout is set by ZTM1-0
bits.
When the control register is written from µP, the zero crossing counter for L/R channels commonly is reset and its
counter starts. When the signal detects zero crossing or zero crossing timeout, the written value from µP becomes a valid
for the first time.
In case of writing to the control register continually, the control register should be written by an interval more than zero
crossing timeout. If an appointed interval is written, there is possible to the different value the IPGA value of L/R
channels. For example, when the present IPGA value is updated by zero crossing detection in a channel of one side and
other channel is not updated, if the new data is written in IPGA, the updated channel is keeping the last IPGA value and
other channel is updated to a new IPGA value by the last zero crossing counter. Therefore, zero crossing counter does
not reset when the zero crossing detection is waiting.
[IPGA Gain after completing ALC operation]
The IPGA gain changed by ALC operation is not reflected to the IPGA register. Therefore, when completing ALC
operation (ALC bit; “1” Æ “0”), the IPGA register is different from the actual gain of IPGA. The value should be
re-written to the IPGA register in order to set the actual gain of IPGA with a register value.
[Operation of IPGA at power-down by the control register]
Gain of IPGA0 and IPGA1 is reset when PM1-0 bits are “00”, and then IPGA operation starts from the default value
after exiting PM1-0 bits = “00”. When IPGA6-0 bits are read, the register values written by the last write operation are
read out regardless the actual gain.
[Operation of IPGA when the number of IPGA channels is changed]
When the number of IPGA channels is changed, PM1-0 bits should be done via “00”. If PM1-0 bits are not done via
“00”, there is a possibility that gain between IPGA0 and IPGA1 is different. However, powered-up all channels become
the same gain when IPGA value is written at ALC disabled state (ALC bit = “0”) or the ALC Limiter/Recovery
operation is done.
MS0067-E-02
- 27 -
2004/12