AK4563A Datasheet, PDF (35/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
„ FADEOUT Mode
In FADEOUT mode, the present IPGA value is decreased until the MUTE state when FDOUT bit changes from “0” to
“1”. This operation is always detected by the zero crossing operation.
If the large signal is input to the ALC circuit during the FADEOUT operation, the ALC limiter operation is done.
However a total time of the FADEOUT operation is the same time, even if the limiter operation is done. The period of
FADEOUT is set by FDTM1-0 bits, a number of step can be set by FDATT bit.
When FDOUT bit changes into “0” during the FADEOUT operation, the ALC operation start from the preset IPGA
value.
When FDOUT and ALC bits change into “0” at the same time, the FADEOUT operation stops and the IPGA becomes the
value at that time.
NOTE: When FDIN and FDOUT bits are “1”, FDOUT operation is enabled.
IPGA Output
ALC bit
FDOUT bit
(2)
(1)
(3)
(4) (5) (6) (7) (8)
Figure 22. Example for controlling sequence in FADEOUT operation
(1) WR (FDOUT = “1”): The FADEOUT operation starts. Then ALC bit should be always “1”.
(2) FADEOUT time can be set by FDTM1-0 and FDATT bits.
During the FADEIN operation, the zero crossing timeout period is ignored and becomes the same as the FADEIN
period.
E.g. FDTM1-0 = 32ms, FDATT = 1step
(96 x FDTM1-0) / FDATT = 96 x 32ms / 1 = 3.07s
(3) The FADEOUT operation is completed. The IPGA value is the MUTE state. If FDOUT bit is keeping “1”, the IPGA
value is keeping the MUTE state.
(4) Analog and digital outputs mutes externally. Then the IPGA value is the MUTE state.
(5) WR (ALC = FDOUT = “0”): Exit the ALC and FADEOUT operations
(6) WR (IPGA): The IPGA value changes the initial value (exiting MUTE state).
(7) WR (ALC = “1”, FDOUT = “0”): The ALC operation restarts. But the ALC bit should not write until completing zero
crossing operation of IPGA.
(8) Release a mute function of analog and digital outputs externally.
MS0067-E-02
- 35 -
2004/12