AK4563A Datasheet, PDF (12/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
Power Supply
PDN pin
PDN pin may be “L” at power-up.
ADC Internal
State
PD
4128/fs
INIT
GD
AIN
SDTO0,1
DAC Internal
State
SDTI
AOUT
Control register
“0”data
PD
GD (1)
(4)
INIT-1
INIT-2
W rite to register
Read from register
External clocks
Inhibit-1 Inhibit-2
Inhibit-1
Normal
PM
GD (1)
4128/fs
INIT
Normal
GD
Norm al
(2)
(3) “0”data
Idle Noise
PM
(1)
Norm al
GD (1)
“0”data
(4)
GD (1)
Normal
Normal
Normal
INIT-2
Norm al
(5)
The clocks may be stopped.
Figure 8. Power-up/Power-down Timing Example
• INIT:
Initializing. At this time, STAT bit is “0”. When this flag becomes “1”, INIT process has completed.
IPGA0 and IPGA1 are MUTE state.
• PD:
Power-down state. ADC is output “0”, analog output of DAC goes floating.
• PM:
Power-down state by operating Power Management bit
• INIT-1: Initializing all registers.
• INIT-2: Initializing read only registers in control registers.
• Inhibit-1: Inhibits writing and reading to all control registers.
• Inhibit-2: Inhibits writing to all control registers.
Note: Please refer to “explanation of register” about the condition of each register.
(1) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(2) If the analog signal does not be input, the digital outputs have the op-amp of input and some noise in ADC.
(3) ADC data is “0” data at power-down.
(4) A few noise occurs at the “↓ ↑” of PDN signal. Please mute the analog output externally if the noise influences
the system application.
(5) When the external clocks are stopped, the AK4563A should be in the power-down mode (PDN pin = “L” or
PM5-0 bit = “0”) .
MS0067-E-02
- 12 -
2004/12