AK4563A Datasheet, PDF (29/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
FUNCTION DETAIL
„ ALC Operation
1. ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch in IPGA0 and IPGA1 exceed ALC limiter detection level
(LMTH), IPGA value is attenuated by ALC limiter ATT step (LMAT1-0) automatically. Then the IPGA value is changed
commonly for L/R channels in IPGA0 and IPGA1. Timeout period is set by LTM1-0 bits. The operation for attenuation is
done continuously until the input signal level becomes LMTH or less. After finishing the operation for attenuation, if
ALC bit does not change into “0”, the operation of attenuation repeats when the input signal level exceed LMTH.
When FR bit is “0”, the ALC operation corresponds to the impulse noise in additional to the ALC operation of AK4516A.
Then if the impulse noise is supplied at ZELMN = “0”, the ALC recovery operation becomes the faster period than a set
of ZTM1-0 bits. In case of ZELMN = “1”, it becomes the same period as LTM1-0 bits.
When FR bit is “1”, the ALC operation in AK4563A is the same as AK4516A’s.
[Explanation for ALC operation]
Limiter starts
ATT Level (LMAT1-0)
Limiter Detection Level(LMTH)
ATT Level (LMAT1-0)
ATT Level (LMAT1-0)
(1) 2dB
Recovery Waiting Counter
Reset Level (LMTH)
Limiter Update Period (LTM1-0)
Limiter finish
Figure 16. Disable ALC zero crossing detection (ZELMN = “1”)
(1) When the signal is input between 2dB, the AK4563A does not operate the ALC limiter and recovery.
MS0067-E-02
- 29 -
2004/12