AK4563A Datasheet, PDF (28/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
Addr
08H
09H
Register Name
Lch Peak Hold
Rch Peak Hold
R/W
RESET
D7
PHL7
PHR7
D6
PHL6
PHR6
D5
PHL5
PHR5
D4
D3
PHL4 PHL3
PHR4 PHR3
RD
00H
D2
PHL2
PHR2
D1
PHL1
PHR1
D0
PHL0
PHR0
PHL7-0: Lch Peak Hold (Absolute Value)
PHR7-0: Rch Peak Hold (Absolute Value)
The peak data is output from ADC0, it is held L/R independently.
These registers are reset by reading from µP.
20 x log ₁₀ [(Data) / 256)] < Peak Level [dB] ≤ 20 x log ₁₀ [(Data+1) / 256)]
Data
Peak Level
FFH
0.0dB ∼ -0.034 dB
FEH
-0.034dB ∼ -0.068dB
FDH
-0.068dB ∼ -0.102dB
•
•
02H
-38.62dB ∼ -42.14dB
01H
-42.14dB ∼ -48.16dB
00H _{-48.16dB ∼ -∞(infinity)}
Table 16. Peak Level
These registers are reset on the following any conditions.
- PDN pin = “L”
- PM2 = PM3 = “0”
MS0067-E-02
- 28 -
2004/12