AK4563A Datasheet, PDF (16/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Input Select
Power Management
Mode Control
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Operation Mode
Input PGA Control
Peak Hold Lch
Peak Hold Rch
D7
0
0
0
FDTM1
0
0
0
0
PHL7
PHR7
D6
0
0
0
FDTM0
0
REF6
0
IPGA6
PHL6
PHR6
D5
0
PM5
0
ZTM1
LMAT1
REF5
ZELMN
IPGA5
PHL5
PHR5
D4
0
PM4
FS
ZTM0
LMAT0
REF4
FR
IPGA4
PHL4
PHR4
D3
LINE
PM3
DIF1
WTM1
FDATT
REF3
STAT
IPGA3
PHL3
PHR3
D2
EXT
PM2
DIF0
WTM0
RATT1
REF2
FDIN
IPGA2
PHL2
PHR2
D1
INT1
PM1
DEM1
LTM1
RATT0
REF1
FDOUT
IPGA1
PHL1
PHR1
D0
INT0
PM0
DEM0
LTM0
LMTH
REF0
ALC
IPGA0
PHL0
PHR0
„ Register Definitions
The following condition can not read and write all registers.
* PDN pin = “L”
Addr
00H
Register Name
Input Select
R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
LINE EXT INT1 INT0
R/W
0
0
0
0
0
0
1
1
INT0: Select ON/OFF of INTL0 and INTR0 (0: OFF, 1: ON)
INT1: Select ON/OFF of INTL1 and INTR1 (0: OFF, 1: ON)
EXT: Select ON/OFF of EXTL and EXTR (0: OFF, 1: ON)
LINE: Select ON/OFF of LIN and RIN (0:OFF, 1:ON)
When LINE bit is “1”, INT0, INT1 and EXT bits are ignored.
Gain tables of IPGA0 and IPGA1 are changed by LINE bit.
When LINE bit is “1”, gain table of IPGA becomes LINE side. But IPGA1 becomes mute state because it does not
have a LINE table.
When INT0 and EXT bits change into “1” at the same time, input signals are mixed by Gain 0dB.
MS0067-E-02
- 16 -
2004/12