AK4563A Datasheet, PDF (26/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
Addr
07H
Register Name
Input PGA Control
R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
0
IPGA6 IPGA5 IPGA4 IPGA3 IPGA2 IPGA1 IPGA0
R/W
0
28H
IPGA6-0: Input Analog PGA; 97 levels; Commonly Lch and Rch of IPGA0 and IPGA1.
The IPGA value should be the same or smaller than REF value before the ALC1 operation including the
FADEIN/FADEOUT operation.
When IPGA gain is changed, IPGA6-0 bits should be written while PM1-0 bits are not “00” and ALC bit is
“0”. (refer to “Operation of IPGA” description)
DATA
60H
5FH
5EH
•
28H
27H
•
19H
18H
17H
16H
•
11H
10H
0FH
0EH
•
05H
04H
03H
02H
01H
00H
GAIN(dB)
Step
MIC
LINE
+28.0
+6.0
+27.5
+5.5
+27.0
+5.0
•
•
+0.0
-22.0
0.5dB
-0.5
-22.5
•
•
-7.5
-29.5
-8.0
-30.0
-9.0
-31.0
-10.0
•
-32.0
•
1dB
-15.0
-37.0
-16.0
-38.0
-18.0
-40.0
-20.0
-42.0
•
•
2dB
-38.0
-60.0
-40.0
-62.0
-44.0
-48.0
-66.0
-70.0
4dB
-52.0
-74.0
MUTE
MUTE
Table 15. Input Gain Setting
There is not LINE table in IPGA1
IPGA value is reset at PM1-0 = “00”.
Level
73
8
12
3
1
MS0067-E-02
- 26 -
2004/12