AK4563A Datasheet, PDF (21/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
Addr
03H
Register Name
Timer Select
R/W
RESET
D7
D6
FDTM1 FDTM0
0
0
D5
ZTM1
0
D4
D3
ZTM0 WTM1
R/W
0
0
D2
WTM0
0
D1
LTM1
0
D0
LTM0
1
LTM1-0: ALC Limiter Period
The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is
done by the period specified by LTM1-0 bit.
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
LTM1
LTM0
Period
0
0
63µs
0
1
125µs ^RESET
1
0
250µs
1
1
500µs
Table 6. ALC Limiter Operation Period
WTM1-0: ALC Recovery Waiting Period
A period of recovery operation when any limiter operation does not during ALC operation.
Recovery operation is done at period set by WTM1-0 bits.
When the input signal level exceeds auto recovery waiting counter reset level set by LMTH bit, the auto
recovery waiting counter is reset.
The waiting timer starts when the input signal level becomes below the auto recovery waiting counter
reset level.
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
WTM1 WTM0
Period
0
0
8ms
RESET
0
1
16ms
1
0
64ms
1
1
512ms
Table 7. ALC Recovery Operation Waiting Period
ZTM1-0: Zero crossing timeout at writing operation by µP and ALC recovery operation
When IPGA of each L/R channels do zero crossing or timeout independently, the IPGA value is
changed by µP WRITE operation or ALC recovery operation.
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
ZTM1
ZTM0
Period
0
0
8ms
RESET
0
1
16ms
1
0
64ms
1
1
512ms
Table 8. Zero Crossing Timeout
MS0067-E-02
- 21 -
2004/12