AK4563A Datasheet, PDF (17/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
Addr
01H
Register Name
Power Management
R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
0
0
PM5 PM4 PM3 PM2 PM1 PM0
R/W
0
0
0
1
1
1
1
1
PM5-0: Power Management (0: Power down, 1: Power up)
PM1-0: IPGA and ALC circuit power control.
After exiting PM1-0 = “00”, IPGA goes reset value. (refer to “Operation of IPGA” description)
PM1
PM0
IPGA1
IPGA0
0
0
OFF
OFF
0
1
OFF
ON
1
0
Lch ON
ON
1
1
ON
ON
Table 2. IPGA and ALC circuit power control
RESET
PM3-2: Power control of ADC
PM3
PM2
ADC1
ADC0
0
0
OFF
OFF
0
1
OFF
ON
1
0
Lch ON
ON
1
1
ON
ON
Table 3. ADC power control
RESET
When the number of ADC channels is changed, PM3-2 bits should be via “00” (ADC0 and
ADC1 are powerd-down.).
For example, in case of changing from 2ch mode (PM3-2 bits = “01”) to 4ch mode (PM3-2 bit
= “11”), PM3-2 bit should change into “11” via “00”.
All Power-down
(PM3-2 = “00”)
2ch Mode
(PM3-2 = “01”)
3ch Mode
(PM3-2 = “10”)
4ch Mode
(PM3-2 = “11”)
Figure 14. ADC Power-up/down Sequence by Power Management bit
In case of exiting all power-down mode (PM3-2 = “00”), the initializing cycle (4128/fs) is
started. Then all outputs of ADC become “0”.
In case of 3ch mode (PM1-0 = “10”, PM3-2 = “10”), right channel of IPGA1 and ADC1 is
powered-down. Then right channel of ADC1 is output “0”.
MS0067-E-02
- 17 -
2004/12