AK4563A Datasheet, PDF (25/39 Pages) Asahi Kasei Microsystems – Low Power 16bit 4ch ADC & 2ch DAC with ALC

ASAHI KASEI
[AK4563A]
Addr Register Name
06H Operation Mode
R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
0
0
ZELM
N
FR
STAT FDIN FDOUT ALC
R/W
RD
R/W
0
0
0
0
0
0
0
0
ALC: ALC Enable Flag
0: ALC Disable (RESET)
1: ALC Enable
FDOUT: FADEOUT Enable Flag
0: FADEOUT Disable (RESET)
1: FADEOUT Enable
FDIN: FADEIN Enable Flag
0: FADEIN Disable (RESET)
1: FADEIN Enable
STAT: Status Flag
0: ALC (including FADEIN and FADEOUT) operation or initializing operation (RESET)
1: Manual Mode
STAT bit is “0” during initializing operation after exiting power-down by PDN pin. After the finish of the
initializing operation, STAT bit becomes “1”.
During the ALC operation, STAT bit becomes “1” after the max “1” ATT/GAIN operation is completed by
internal state.
FR: Select ALC operation Mode
0: The ALC operation corresponds to impulse noise. (RESET)
1: The ALC operation is the same as AK4516A
ZELMN: Enable zero crossing detection at ALC Limiter operation
0: Enable (RESET)
1: Disable
In case of ZELMN = “0”, IPGA of each L/R channel do zero crossing or timeout independently, the IPGA
value is changed by the ALC operation. Zero crossing timeout is the same as the ALC recovery operation. In
case of ZELMN = “1”, the IPGA value is changed immediately.
MS0067-E-02
- 25 -
2004/12