AK5701 Datasheet, PDF (58/62 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP 16-Bit Stereo ADC

ASAHI KASEI
[AK5701]
„ ΫϩοΫͷఀࢭ
ADCΛ࢖༻͠ͳ͍৔߹͸ɺϚελΫϩοΫΛఀࢭ͢Δ͜ͱ͕Ͱ͖·͢ɻ
1. PLLϚελϞʔυͷ৔߹
PMPLL bit
(Addr:11H, D0)
M/S bit
(Addr:11H, D1)
MCKO bit
(Addr:16H, D2)
External MCKI
Example:
(1)
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
"H" or "L"
Input
(1) Addr:11H, Data:10H
(2)
(2) Addr:16H, Data:00H
(3)
(3) Stop an external MCKI
Figure 53. Clock Stopping Sequence (1)
<खॱྫ>
(1) PLLͷύϫʔμ΢ϯ: PMPLL=M/S bits = “1” → “0”
(2) MCKOग़ྗͷఀࢭ: MCKO bit = “1” → “0”
(3) ֎෦ΫϩοΫΛࢭΊͯԼ͍͞ɻ
2. PLLεϨʔϒϞʔυ(EXLRCK, EXBCLK pin)ͷ৔߹
PMPLL bit
(Addr:11H, D0)
EXBCLK
EXLRCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
BCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1) Addr:11H, Data:0CH
(2) Stop the external clocks
Figure 54. Clock Stopping Sequence (2)
<खॱྫ>
(1) PLLͷύϫʔμ΢ϯ: PMPLL bit = “1” → “0”
(2) ֎෦ΫϩοΫΛࢭΊͯԼ͍͞ɻ
* εϨʔϒ&όΠύεϞʔυ΋ಉ༷ͷखॱͰ͢ɻ
MS0404-J-00
- 58 -
2005/08