AK5701 Datasheet, PDF (40/62 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP 16-Bit Stereo ADC

ASAHI KASEI
[AK5701]
„ γϦΞϧίϯτϩʔϧΠϯλϑΣʔε
Ϩδελઃఆ͸3ઢࣜγϦΞϧI/Fϐϯ(CSN, CCLK, CDTI)Ͱॻ͖ࠐΈΛߦ͍·͢ɻCSP pinͷઃఆʹΑΓCSN
pinͷۃੑͱChip address͕੾ΓସΘΓ·͢ɻ
1) CSP pin = “L”ͷͱ͖
I/F্ͷσʔλ͸Chip address (2bits, “10”ݻఆ), Read/Write (1bit, “1”ݻఆ), Register address (MSB first, 5bits) ͱ
Control Data (MSB first, 8bits)Ͱߏ੒͞Ε·͢ɻσʔλૹ৴ଆ͸CCLKͷ “↓”Ͱ֤ϏοτΛग़ྗ͠ɺड৴ଆ͸ “↑”
ͰऔΓࠐΈ·͢ɻσʔλͷॻ͖ࠐΈ͸CSNͷ “↓”ޙ16ճ໨ͷCCLK “↑”Ͱ༗ޮʹͳΓ·͢ɻCCLKͷΫϩοΫ
εϐʔυ͸7MHz (max)Ͱ͢ɻPDN pin = “L”ͰϨδελͷ஋͸Ϧηοτ͞Ε·͢ɻ
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1” “0” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 41. γϦΞϧίϯτϩʔϧΠϯλϑΣʔελΠϛϯά(CSP pin = “L”)
2) CSP pin = “H”ͷͱ͖
I/F্ͷσʔλ͸Chip address (2bits, “01”ݻఆ), Read/Write (1bit, “1”ݻఆ), Register address (MSB first, 5bits) ͱ
Control Data (MSB first, 8bits)Ͱߏ੒͞Ε·͢ɻσʔλૹ৴ଆ͸CCLKͷ “↓”Ͱ֤ϏοτΛग़ྗ͠ɺड৴ଆ͸ “↑”
ͰऔΓࠐΈ·͢ɻσʔλͷॻ͖ࠐΈ͸CSNͷ “↑”ޙ16ճ໨ͷCCLK “↑”Ͱ༗ޮʹͳΓ·͢ɻCCLKͷΫϩοΫ
εϐʔυ͸7MHz (max)Ͱ͢ɻPDN pin = “L”ͰϨδελͷ஋͸Ϧηοτ͞Ε·͢ɻ
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“0” “1” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “0”, C0 = “1”); Fixed to “01”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 42. γϦΞϧίϯτϩʔϧΠϯλϑΣʔελΠϛϯά(CSP pin = “H”)
MS0404-J-00
- 40 -
2005/08