AK5701 Datasheet, PDF (23/62 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP 16-Bit Stereo ADC

ASAHI KASEI
[AK5701]
EXLRCK or EXBCLKΑΓೖྗͷ৔߹͸ɺFS3, FS2 bitͰαϯϓϦϯάप೾਺ͷઃఆΛߦͬͯԼ͍͞(Table 6)ɻ
Mode ^{FS3 bit FS2 bit}
FS1 bit
FS0 bit
Sampling Frequency
Range
0
0
0
Don’t care Don’t care
7.35kHz ≤ fs ≤ 12kHz
1
0
1
Don’t care Don’t care
12kHz < fs ≤ 24kHz
2
1
Don’t care Don’t care Don’t care
24kHz < fs ≤ 48kHz Default
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=EXLRCK/EXBCLK
„ PLLͷΞϯϩοΫʹ͍ͭͯ
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
͜ͷϞʔυͰ PMPLL bit = “0” Æ “1”ޙͨ͠ʹPLL͕ϩοΫ͢Δ·ͰͷؒɺBCLKͱLRCK͸ “L”Λग़ྗɺMCKO
bit = “1”ͷͱ͖MCKO pin͔Β͸ਖ਼ৗͰͳ͍प೾਺ͷΫϩοΫ͕ग़ྗ͞Ε·͢ɻMCKO bit = “0”ͷ৔߹͸ɺ
MCKO pin͸ “L”Λग़ྗ͠·͢ɻ(See Table 7)
DSP Mode 0, 1ʹ͓͍ͯɺPMPLL bit = “0” Æ “1”ઃఆʹΑΓPLL͕ϩοΫͨ͠ޙɺBCLKͱLRCK͸Lchͷσʔ
λʹରԠͯ͠ग़ྗΛ։࢝͠·͢ɻDSP Mode 0, 1ͰMSBS bit = “0”, BCKP bit = “1”·ͨ͸MSBS bit = “1”, BCKP
bit = “0”ͷ৔߹ɺBCLKग़ྗ։࢝ͷ1ൃ໨ͷ “H”෯͕2ൃ໨Ҏ߱ʹൺ΂ͯ1/(256fs)͚ͩ୹͘ͳΓ·͢ɻ
αϯϓϦϯάप೾਺Λมߋ͢Δ৔߹͸Ұ౓PMPLL bit = “0”ʹ͢Δ͜ͱͰΞϯϩοΫঢ়ଶͷෆఆͳBCLK,
LRCKΛग़ྗͤͣ͞ʹ “L”Λग़ྗͤ͞Δ͜ͱ͕Ͱ͖·͢ɻ
PLL State
PMPLL bit “0” Æ “1”௚ޙ
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
ෆఆ
BCLK pin
“L” Output
LRCK pin
“L” Output
PLL Unlock ࣌(ه্Ҏ֎)
“L” Output
ෆఆ
ෆఆ
ෆఆ
PLL Lock ࣌
“L” Output
See Table 9
See Table 10
1fs Output (*)
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
* DSP Mode 1ͷͱ͖ɺLRCK͸2fsͰ͢ɻ
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
͜ͷϞʔυͰ͸ PMPLL bit = “0” Æ “1”ޙͨ͠ʹPLL͕ϩοΫ͢Δ·ͰͷؒɺMCKO͔Β͸ਖ਼ৗͰͳ͍प೾਺
ͷΫϩοΫ͕ग़ྗ͞Ε·͢ɻͦͷޙɺPLL͕ϩοΫ͢ΔͱMCKO pin͔ΒTable 9Ͱબ୒͞ΕͨΫϩοΫ͕ग़ྗ
͞Ε·͢ɻୠ͠ɺPLL͕ΞϯϩοΫʹͳͬͨ৔߹ɺADC͔Β͸ਖ਼ৗͳσʔλ͕ग़ྗ͞Ε·ͤΜɻ
PLL State
PMPLL bit “0” Æ “1”௚ޙ
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
ෆఆ
PLL Unlock ࣌(ه্Ҏ֎)
“L” Output
ෆఆ
PLL Lock ࣌
“L” Output
See Table 9
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MS0404-J-00
- 23 -
2005/08