AK5701 Datasheet, PDF (21/62 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP 16-Bit Stereo ADC

ASAHI KASEI
[AK5701]
ػೳઆ໌
„ γεςϜΫϩοΫ
֎෦ͱͷI/FϞʔυ͸ҎԼͷ5௨Γͷํ๏͕͋Γ·͢ɻ(See Table 1 and Table 2.)
Mode
PMPLL bit
M/S bit PLL3-0 bits
Figure
PLL Master Mode (Note 24)
1
1
See Table 4 Figure 19
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
0
See Table 4 Figure 21
PLL Slave Mode 2
(PLL Reference Clock: EXLRCK or EXBCLK pin)
1
0
See Table 4 Figure 20
EXT Slave Mode
0
0
x
Figure 22
EXT Master Mode (Note 25)
0
1
x
Figure 23
Note 24. PLL Master Modeʹઃఆ͢ΔաఔͰɺM/S bit = “1”, PMPLL bit = “0”, MCKO bit = “1”ͷͱ͖MCKO pin
͔Βਖ਼ৗͰͳ͍प೾਺ͷΫϩοΫ͕ग़ྗ͞Ε·͢ɻ
Note 25. EXT Master ModeͰ࢖༻͢Δ৔߹ɺFigure 49ͷखॱͰઃఆͯ͠Լ͍͞ɻ
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
MCKO pin
MCKI pin
BCLK pin,
EXBCLK pin
PLL Master Mode
0
1
“L”
PS1-0 bitsÍ°
બ୒
PLL3-0 bits
Ͱબ୒
BCLK pin
(BCKO1-0
bitsͰબ୒)
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
0
“L”
1
PS1-0 bitsÍ°
બ୒
PLL3-0 bits EXBCLK pin
Ͱબ୒
(≥ 32fs)
PLL Slave Mode
(PLL Reference Clock: EXLRCK
0
EXBCLK pin
“L”
GND
(PLL3-0 bits
or EXBCLK pin)
Ͱબ୒)
EXT Slave Mode
0
“L”
FS1-0 bitsÍ° EXBCLK pin
બ୒
(≥ 32fs)
EXT Master Mode
0
“L”
FS1-0 bitsÍ°
બ୒
BCLK pin
(BCKO1-0
bitsͰબ୒)
Table 2. Clock pins state in Clock Mode
Note 26. PLL Master ModeͰDSP Mode 1ͷͱ͖ɺLRCK͸2fsͰ͢ɻ
LRCK pin,
EXLRCK pin
LRCK pin
(1fs)
(Note 26)
EXLRCK pin
(1fs)
EXLRCK pin
(1fs)
EXLRCK pin
(1fs)
LRCK pin
(1fs)
„ ϚελϞʔυͱεϨʔϒϞʔυͷ੾Γସ͑
ϚελϞʔυͱεϨʔϒϞʔυͷ੾Γସ͑͸M/S bitͰߦ͍·͢ɻ“1”ͰϚελϞʔυɺ“0”ͰεϨʔϒϞʔυ
Ͱ͢ɻAK5701͸ύϫʔμ΢ϯ࣌ (PDN pin = “L”)ɺͼٴύϫʔμ΢ϯղআޙ͸εϨʔϒϞʔυͰ͢ɻύϫʔ
μ΢ϯղআޙɺM/S bitΛ “1”ʹมߋ͢Δ͜ͱͰϚελϞʔυʹͳΓ·͢ɻ
M/S bit
0
1
Mode
࢖༻͢Δϐϯ
Slave Mode
Master Mode
EXBCLK, EXLRCK
BCLK, LRCK
Table 3. Select Master/Salve Mode
Default
MS0404-J-00
- 21 -
2005/08