AK4584_01 Datasheet, PDF (51/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
1. Grounding and Power Supply Decoupling
The AK4584 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and PVDD are
usually supplied from the analog supply in the system. Alternatively if AVDD, DVDD and PVDD are supplied separately,
the power up sequence is not critical. TVDD is a power supply pin to interface with external ICs and is supplied from the
digital supply in the system. AVSS, DVSS and PVSS of the AK4584 must be connected to analog ground plane.
System analog ground and digital ground should be connected together near to where the supplies are brought onto the
printed circuit board. Decoupling capacitors should be as near to the AK4584 as possible, with the small value ceramic
capacitor being the nearest.
2. Voltage Reference Inputs
The differential voltage between VREF and AVSS sets the analog input/output range. VREF pin is normally connected to
AVDD with a 0.1µF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with
a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be
drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order
to avoid unwanted coupling into the AK4584.
3. Analog Inputs
ADC inputs are single-ended and the input resistance is 10kΩ (typ). The input signal range scales with the supply voltage
and nominally 0.6 x VREF Vpp (typ). Usually the input signal is AC coupled with capacitor. The cut-off frequency is fc =
1/(2πRC). The AK4584 can accept input voltages from AVSS to AVDD. The ADC output data format 2’s compliment.
The internal HPF removes the DC offset.
The AK4584 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK4584 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are single-ended and centered around the VCOM voltage. The input signal range scales with the supply
voltage, nominally 0.6 x VREF Vpp. The DAC input data format is 2’s complement. The output voltage is a positive full
scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is 0V for 000000H(@24bit).
The internal analog filters remove most of the out-of-band noise generated by the DAC’s delta-sigma modulator.
5. XTI pin and XTO pin
(1) C depends on the X’tal (typ. 10 ∼ 40pF).
(2) When an external clock is supplied, the XTO pin is left floating and the clock source is connected to the XTI pin. The
input voltage should not exceed DVDD. When applying a CMOS level signal to the XTI pin, when XTALE pin = “L”
and PDN pin = “L”, the XTI pin is fixed to “L”. The means that the XTI pin can accept a CMOS level clock as well as
TTL level clock. The only restriction to this is the clock high level must be equal to or greater than 40% DVDD, not to
exceed DVDD. The low value of the clock must be 30% DVDD or lower, not to drop below DGND.
(3) When the XTI and the XTO pins are not used, leave the XTO pin floating and connect the XTI pin to DVSS.
MS0118-E-00
- 51 -
2001/11