AK4584_01 Datasheet, PDF (37/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
„ Register Definitions
Addr Register Name
D7
D6
D5
00H Power Down Control
0
0
0
R/W
RD
RD
RD
Default
0
0
0
D4
TEST
R/W
1
D3
PWDITN
R/W
1
D2
PWVRN
R/W
1
D1
PWADN
R/W
1
D0
PWDAN
R/W
1
PWDAN: DAC Power Down
0: Power down
1: Power up
“0” powers down only the DAC section and then places LOUT and ROUT immediately to a high-Z state. The
OATTs also go to “FFH”. But the contents of all register are not initialized and enabled to write to the registers.
After exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H).
The analog output should be muted externally as some pop noise may occur when entering to and exiting from
this mode.
PWADN: ADC Power Down
0: Power down
1: Power up
“0” powers down only the ADC section and then the SDTO goes “L” immediately. The IPGAs also go “00H”.
But the contents of all register are not initialized and enabled to write to the registers. After exiting the power
down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, ADC output
“0” during first 516 LRCK cycles.
PWVRN: VREF Power Down
0: Power down
1: Power up
“0” powers down all sections and then both ADC and DAC do not operate. The contents of all register are not
initialized and enabled to write to the registers. When PWADN bit and PWDAN bit go “0” and PWVRN bit
goes “1”, only VREF section can be powered up.
PWDITN: DIT Power Down
0: Power down
1: Power up
“0” powers down only the DIT section. Therefore, TX3 pin output is disabled . TX1 pin and TX2 pin can
output the biphase signal. The contents of all register are not initialized and enabled to write to the registers.
TEST: TEST bit
Must be fixed to “1”
MS0118-E-00
- 37 -
2001/11