AK4584_01 Datasheet, PDF (38/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
Addr
01H
Register Name
Reset Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
RSTADN RSTDAN
RD
RD
RD
RD
RD
RD
R/W
R/W
0
0
0
0
0
0
0
0
RSTDAN: DAC Reset
0: Reset
1: Normal Operation
“0” resets the internal timing and immediately drives the LOUT and ROUT to the VCOM voltage. The OATTs
go to “FFH”. The contents of all registers are unaffected but are write-enabled. After exiting the power down
mode, the OATTs fade in based on the values of the control registers (06H & 07H). The analog outputs should
be muted externally as some pop noise may occur when entering to and exiting from this mode.
RSTADN: ADC Reset
0: Reset
1: Normal Operation
“0” resets the internal timing and SDTO immediately goes to “L”. The IPGAs go to “00H”. The contents of all
registers are unaffected but are write-enabled. After exiting the power down mode, the IPGAs fade in based on
the values of the control registers (04H & 05H). At that time, ADC output is “0” during first 516 LRCK cycles.
Addr Register Name
D7
D6
D5
D4
D3
02H Clock and Format Control
0
0
0
DIF2 DIF1
R/W
RD
RD
RD
R/W
R/W
Default
0
0
0
0
1
DFS1-0: Sampling Speed Control (see Table 6)
Initial values are “00”.
DIF2-0: Audio Data Interface Modes (see Table 16)
Initial values are “010” (24bit MSB justified for both ADC and DAC).
D2
DIF0
R/W
0
D1
DFS1
R/W
0
D0
DFS0
R/W
0
MS0118-E-00
- 38 -
2001/11