AK4584_01 Datasheet, PDF (36/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
Register Name
Power Down Control
Reset Control
Clock & Format Control
Deem & Volume Control
Lch IPGA Control
Rch IPGA Control
Lch OATT Control
Rch OATT Control
In/Out Source Control
Clock Mode Control
DIR Control
DIT Control
INT0 Mask
INT1 Mask
Receiver Status 0
Receiver Status 1
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
TX Channel Status Byte 0
TX Channel Status Byte 1
TX Channel Status Byte 2
TX Channel Status Byte 3
TX Channel Status Byte 4
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
D7
0
0
0
MSDTO
IPGL7
IPGR7
ATTL7
ATTR7
0
OCKS1
0
0
MAT0
MAT1
AUTO
0
CR7
CR15
CR23
CR31
CR39
CT7
CT15
CT23
CT31
CT39
PC7
PC15
PD7
PD15
D6
0
0
0
SMUTE
IPGL6
IPGR6
ATTL6
ATTR6
0
OCKS0
CS12
0
MDTS0
MDTS1
DTSCD
0
CR6
CR14
CR22
CR30
CR38
CT6
CT14
CT22
CT30
CT38
PC6
PC14
PD6
PD14
D5
0
0
0
DZFE
IPGL5
IPGR5
ATTL5
ATTR5
DAC1
ICKS1
OPS1
TX3E
MAN0
MAN1
AUDION
0
CR5
CR13
CR21
CR29
CR37
CT5
CT13
CT21
CT29
CT37
PC5
PC13
PD5
PD13
D4
TEST
0
DIF2
ZCEI
IPGL4
IPGR4
ATTL4
ATTR4
DAC0
ICKS0
OPS0
TX2E
MV0
MV1
VDIR
0
CR4
CR12
CR20
CR28
CR36
CT4
CT12
CT20
CT28
CT36
PC4
PC12
PD4
PD12
D3
PWDITN
0
DIF1
ZTM1
IPGL3
IPGR3
ATTL3
ATTR3
PCM1
CM1
IPS1
TX1E
MPE0
MPE1
PEM
FS3
CR3
CR11
CR19
CR27
CR35
CT3
CT11
CT19
CT27
CT35
PC3
PC11
PD3
PD11
D2
PWVRN
0
DIF0
ZTM0
IPGL2
IPGR2
ATTL2
ATTR2
PCM0
CM0
IPS0
UDIT
MUL0
MUL1
UNLOCK
FS2
CR2
CR10
CR18
CR26
CR34
CT2
CT10
CT18
CT26
CT34
PC2
PC10
PD2
PD10
D1
PWADN
RSTADN
DFS1
DEM1
IPGL1
IPGR1
ATTL1
ATTR1
DIT1
XTL1
EFH1
VDIT
MPR0
MPR1
PAR
FS1
CR1
CR9
CR17
CR25
CR33
CT1
CT9
CT17
CT25
CT33
PC1
PC9
PD1
PD9
D0
PWDAN
RSTDAN
DFS0
DEM0
IPGL0
IPGR0
ATTL0
ATTR0
DIT0
XTL0
EFH0
TCH
MFS0
MFS1
FS
FS0
CR0
CR8
CR16
CR24
CR32
CT0
CT8
CT16
CT24
CT32
PC0
PC8
PD0
PD8
PDN = “L” resets the registers to their default values.
„ Control Register Setup Sequence
When the PDN pin goes from “L” to “H” upon power-up etc., the AK4584 will be ready for normal operation by the next
sequence. In this case, all control registers are set to initial values and the AK4584 is in the reset state.
(1) Set the clock mode and the audio data interface mode.
(2) Cancel the reset state by setting RSTADN bit or RSTDAN bit to “1”. Refer to Control Register (01H).
(3) ADC output and DAC output should be muted externally until canceling each reset state, since in master mode there
is a possibility that the frequency and duty cycle of LRCK and BICK outputs may become distorted.
The clock mode should be changed after setting RSTADN bit and RSTDAN bit to “0”. At that time, the ADC and DAC
outputs should be muted externally since in master mode, there is a possibility that the frequency and duty of LRCK and
BICK outputs may become distorted.
MS0118-E-00
- 36 -
2001/11